1. Field of the Invention
The present invention relates generally to phase locked frequency synthesizers, and in particular to phase locked loops that suppress the leakage of spurious energy, phase locked loops that switch bandwidth, or phase locked loops that require low phase offset.
2. Discussion of the Related Art
A phase locked loop (PLL) is a negative feedback system that maintains a constant phase and zero frequency difference between a variable frequency and a reference frequency. Conventional PLL""s include a phase detector element to compare the frequency and phase of an oscillator to that of the reference frequency. The oscillator is then controlled to maintain the constant phase and frequency difference.
The speed with which the phase locked loop can transition from one lock point (or frequency) to the next is a limiting performance factor in many applications. The phase locked loop is therefore often designed with two or more control system bandwidths (or loop transfer functions): one is a very wide bandwidth that is used to rapidly tune the synthesizer away from the last locked frequency toward the new frequency, and another is the final narrow bandwidth that is used to provide stable low noise operation during the time that the new frequency is being supplied and the communication channel is active.
Generally, the PLL control system bandwidth must be sufficiently wide to rapidly tune the PLL away from the last locked frequency toward the new frequency. One common type of PLL uses an active integrator in the forward path to what is known as a second order control system. However, construction of an active integrator typically requires the use of a wideband operational amplifier to provide a sufficiently large PLL bandwidth. The wideband op-amp preferably includes performance characteristics such as low input bias current and voltage offset to reduce the effects of operating with offset phase caused by high bias current or offset voltage. Operating with offset phase may cause undesirable effects such as increased spurious energy from the phase detector or difficulty in smoothly switching between wideband and narrowband tracking modes. Conventional PLLs employ wideband FET input op-amps to reduce the effects of offset phase. However, wideband FET input op-amps are very expensive. A less expensive alternative to a FET input op-amp is a bipolar input op-amp. However, bipolar input op-amps universally have large input bias currents and at least modest offset voltages which result in operating with offset phase.
The phase locked loop system and method provides a system and method for generating a variable output frequency signal. The phase locked loop includes a controlled oscillator to generate the variable output frequency signal in response to a tune signal. A phase detector generates an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit is coupled to the loop filter. In response to the error signal the offset cancellation circuit cancels errors associated with the loop filter.
For a more complete understanding of the invention, its objects and advantages, reference may be had to the following specification and to the accompanying drawings.